+++ Steve Wiseman [04-09-17 01:24 +0100]:
> 16/09/2004 16:05:35, "David Bisset" 
> <david_bisset@itechnic.co.uk> wrote:
> 
> Aaah, the CPLD. Therein hangs a tale. It's likely to be a softloaded 
> FPGA this time. More pins, more funtionality, more room for 
> bespoke innards, less cost. However, static current is much higher 
> (mA, not uA), so it'll need to be powered down for sleep modes, 
> and reconfigured on resume. No great hardship. (I wanted to do 
> this for Balloon2, but couldn't, since the PLD was needed to mess 
> with the reset and power control lines. Things are easier with 
> PXA27x, and the FPGA is only now for frippery like NAND, SM, CF 
> and the bus interface. (5V signalling on the backplane interface - 
> very tricky, and a waste of good bus buffers. Discuss). 

An alarm rings...

but the 'frippery' like the NAND is where all the code is going to be
running from, and that code needs to do the 'reprogram the FPGA on wake-up',
which sounds like a problem. Or is the point that this code will be living
in the bootloader which will have to remain in nor precisely because you
can't talk to the NAND on boot.

Hmm - and are you considering moving to 2K page/16bit nand (which needs
YAFFS2 for best effect).

YAFFS2 is underway again, after something of a pause whilst Chalres had other
stuff on his mind. Hopefully it'll be ready before balloon3.

Wookey
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