I've just got my sticky hands on a load of guralp-build balloons
containing 1Gig Nand K9F1G08UOA-PCB (instead of the old K9F1208UOB-YCB0T00).

My understanding of the current state of the code is that we might need
changed CPLD code - Chris?

And we need both chip support and YAFFS2 support in both the bootldr and
the kernel. Bootldr currently has chip support, but YAFFS1 support only,
so that needs updating, and the kernel is OK so long as we get the MTD
interface right (see much discussion on YAFFS list).

So, this mail is checking that I'm not duplicating any work in updating
bootldr to yaffs2, and that if CPLD changes are needed can someone send me
the runes?

Wookey
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