Afternoon, chaps. Twiddling my FPGA thumbs here, in anticipation of  
hardware...

Do we have any cycle timings we're aiming for on the PXA bus, so I can  
make sane guesses as to pipeline requirements?

Also - NAND acceleration. NAND performance has been a bit more slothful  
than I'd like up until now - we've never really approached saturating the  
devices. Is there merit in accelerating things in the FPGA, to give you a  
32-bit interface and ECC calculation? Note - this doesn't get you off the  
hook for previous sluggishness, and I'll want to see complete saturation  
of busses from now on :)
(There's also the possibility of a bit of readahead caching, but that's  
rather scary...)

Steve