David Bisset wrote:
> Having recently got the FPGA to program from the Bootldr the answer has to
> be no, although there was a minor hardware fix needed but this is a
> prototype....
> 
> Was your question more generic ie how do you interface Xilinx to PXA?
> Since schematics for L3 aren't available yet it would be difficult to work
> this out from the docs currently on the web.

What I'm most interested in is the choice of interface method given that
the PXA270 allows several [most particularly mapping the FPGA as a
non-burst SRAM, or mapping it as a VLIO device].

The latter is most likely going to be needed if the FPGA gates any slow
hardware since it can assert wait-states (unless you are willing to slow
down the entire memory region mapped to the FPGA via a MSC register).

However there are some quirks using the VLIO mode, such as the fact that
nWE no longer applies (you have to use nPWE for writes, which is normally
used for the pccard interface. Go figure.)

Currently on my device* I'm using the non-burst SRAM model with streaming
data but haven't settled on that as a final solution (application is
still being developed).

-- Chris

* not a balloon obviously, but shares some traits with it. I came across
  this project via a google search.