After some discussions with Nick today, I've just checked in to
subversion some adjustments to bootldr. Again, there's no tag yet since
this isn't an official release.

Firstly, it now auto-detects (in large memory model mode, at least)
whether the board it's running on has 256Mbit or 512Mbit SDRAMs fitted,
so the same bootldr will run on P1, P2 and E1 release boards. I've also,
in passing, confirmed that as long as the correct FPGA image is loaded
into flash, the same bootldr will work with both the XC3S400 and
XC3S1000 FPGAs - the smaller device just ignores configuration data
beyond what it needs.

Secondly, the 'reset' command should now work properly, where it failed
about 50% of the time in the past. A bit of hardware probing showed some
evidence that the board was failing to reboot because the data bus was
jammed in a funny state, which coincided with one bank of SDRAM chips
warming up significantly after a couple of minutes. Now, before letting
the watchdog timer trigger the reset, bootldr goes into a tight loop to
ensure that SDRAM isn't being accessed when the watchdog timer fires. It
seems to have fixed the problem, but I can't help feeling that it
shouldn't happen in the first place. The watchdog timer can't be a lot
of use in the real world if there's a fair chance of the board not
actually rebooting properly.

That's all for now
Chris
-- 
Chris Jones - chris@martin-jones.com
Martin-Jones Technology Ltd, makers of Solidlights
148 Catharine Street, Cambridge, CB1 3AR, UK
Phone +44 (0) 1223 655611 Fax +44 (0) 870 112 3908
http://www.solidlights.co.uk/