Wookey and I came across this problem on Friday: the P2 build of boards,
in current and future use in CUED and elsewhere, have XC3S400 FPGAs
fitted to them. For some reason, the kernel panics during boot if the
FPGA code is built using Xilinx ISE 8.2 (the current version) but not if
it's built using ISE 8.1.

I've now spent several hours trying all possible permutations of
compilers and L3 VHDL versions. Here's the summary of what's what.

The VHDL as released with the P2 build as seen at
http://balloonboard.org/cgi-bin/viewcvs.cgi/balloon/tags/P1-release/vhdl/
builds under ISE 8.1 and works on P2 boards, but has some (now known)
bugs in it. It won't build under ISE 8.2 due to some warnings about
registers not being the right sizes, mostly.

The latest version of the VHDL (the current head in svn) builds OK under
8.2 but the resulting .bin file doesn't work on P2 boards - the kernel
panics during boot.

The latest VHDL _does_ also build under 8.1, and then works fine on P2
boards, so I'm confident that the problem is not caused by the minor
mods to get it all to build under 8.2.

I've tried various things which didn't help: applying the latest patches
to 8.2, cleaning up all the output files to force a rebuild, even
rebuilding the project file from scratch.

At the moment I have no further clue as to what's causing the problem,
but the current workaround is:
- if you're building for the XC3S400 on a P2 board, use ISE 8.1
- if you're building for the XC3S1000 on an E1 board, use ISE 8.1 or 8.2

Chris
-- 
Chris Jones - chris@martin-jones.com
Martin-Jones Technology Ltd, makers of Solidlights
148 Catharine Street, Cambridge, CB1 3AR, UK
Phone +44 (0) 1223 655611 Fax +44 (0) 870 112 3908
http://www.solidlights.co.uk/