We have a system that includes some NAND flash combined together on the
bus (with some CPLD code to make it appear to be a single chip, and take
care of combining the ALE,CLE,nCE lines etc...). That is, the 8 data
bits are combined to give 16, or 32 bits. Thus the chips go from being
2k to 4k or 8k, and the OOB size is expanded similarly. Obviously there
are a few oddities here (such as the bad block marker now being 2 or 4
markers which each need to be checked), but basically it is just a very
large NAND chip.

My question is, would there me a huge amount of work involved in
convincing YAFFS2 to work with a non-standard NAND layout like this?

Thanks,
Andre

-- 
Bluewater Systems Ltd - ARM Technology Solutions Centre

       Andre Renaud                             Bluewater Systems Ltd
Phone: +64 3 3779127 (Aus 1 800 148 751)        Level 17, 119 Armagh St
Fax:   +64 3 3779135                            PO Box 13889
Email: arenaud@bluewatersys.com                 Christchurch
Web:   http://www.bluewatersys.com              New Zealand