On Thursday 08 March 2007 05:35, Johnson, Charles F wrote:
> I'm new to the game regarding flash file systems.  So no, I'm not that
> familiar with the consequences.
> I'm trying to learn enough to keep the hardware designers honest.

Which hardware designers? Board or chip level?
NOR or NAND?

Anyone designing new NAND parts should probably discuss ideas  through ONFI 
(Intel is a member).

If you're designing a board with existing NAND parts:
1) Take care with the WP control. Don't use the power supply regulation flags 
to  yank WP.
2) Provide some "power good" flag that can be read by the drivers to ensure 
that there is going to be sufficient residual power to complete a 
write/erase.
3) Software Hamming ECC is slowish, but very simple to implement in hardware 
with a few gates. As processes change, NAND reliability might reduce further 
which might need Reed Solomon ECC which is more expensive.

There are a bunch more considerations, but those depend very much on 
application and usage models.

-- CHarles

>
>
> Charles Johnson
> Ultra-Mobility Group
> Platform Software Engineering
> Intel Corporation
> charles.f.johnson@intel.com
>
>
> -----Original Message-----
> From: yaffs-bounces@lists.aleph1.co.uk
> [mailto:yaffs-bounces@lists.aleph1.co.uk] On Behalf Of Brad Beveridge
> Sent: Tuesday, March 06, 2007 6:38 PM
> To: Charles Manning
> Cc: yaffs@lists.aleph1.co.uk
> Subject: Re: [Yaffs] Large Flash Support
>
> On 06/03/07, Charles Manning <manningc2@actrix.gen.nz> wrote:
> > On Wednesday 07 March 2007 15:06, Johnson, Charles F wrote:
> > > Can YAFFS2 support the following:
> > >
> > > * Virtual page: 4KB, 8KB or 16KB
>
> I'm sure you're aware, but one downside of large virtual blocks is
> that you will have much greater wastage when a block is marked bad.
>
> Cheers
> Brad
>
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