On 2007-09-21 19:33 +0100, Chris Jones wrote:
> With a little Wookey and Wiki help, attached is the kernel patch to
> enable VGA and SVGA outputs on loon 3. There is a config option under
> System Type -> Intel PXA2xx Implementations -> Balloon 3 LCD
> configuration which allows you to select the display type. This may or
> may not be the right place for it, but it works for me.
> 
> I created the patch using quilt on top of the basic balloon3.patch, so
> that's where it lives in the series.

OK. I'm just incorporating this into the tree. I have a few queries.


> Index: linux-2.6.22.2-pristine/arch/arm/mach-pxa/balloon3.c
> ===================================================================
> --- linux-2.6.22.2-pristine.orig/arch/arm/mach-pxa/balloon3.c	2007-09-21 18:12:05.000000000 +0000
> +++ linux-2.6.22.2-pristine/arch/arm/mach-pxa/balloon3.c	2007-09-21 18:13:05.000000000 +0000
> @@ -281,8 +281,20 @@
>  #endif
>  }
>  
> +// note here that only certain values of pixclock make sense, because the pixel clock
> +// is derived by dividing LCLK (104MHz) by an integer even though it's specified down
> +// to the picosecond. 
> +// The divisor integer must be even if LCCR4_PCCDIV is not set, but can be odd if
> +// LCCR4_PCDDIV is set.
> +// Divisor    pixclock     Pixel clock frequency
> +//   6          57600         17.333MHz
> +//   5          48000         20.8MHz *requires LCCR4_PCDDIV set*
> +//   4          38400         26MHz
> +//   3          28800         34.667MHz *requires LCCR4_PCDDIV set*
> +//   2          19200         52MHz *generally too high to be useful, leaves no DMA bandwidth for anything else *
> +
>  #ifdef CONFIG_BALLOON3_TOPPOLY
> -static struct pxafb_mode_info toppoly_mode __initdata = {
> +static struct pxafb_mode_info balloon3_lcd_mode __initdata = {
>  	.pixclock		= 38000,

It just said above that this should be 38400 - so is 38000 right or
shouold be fixed? I assume the latter.

> +	.lccr4			= 0,

I had to re-do the definition in the relevant struct in pxafb.h for
some reason. It seems traditional to also have a
comment like this one for the LCCR3 register:
   /* The following should be defined in LCCR3
    *      LCCR3_OutEnH or LCCR3_OutEnL    Output enable polarity
    *      LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
    *      LCCR3_Acb(X)                    AB Bias pin frequency
    *      LCCR3_DPC (optional) Double Pixel Clock mode (untested)
    *
    * The following should not be defined in LCCR3
    *      LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
    */

I have no idea which bits should/shouldn't be set in general pxa
terms. I've put:
        /* The following should be defined in LCCR4
         *     LCCR4_PCDDIV (if odd pixclock divisor required)

seem reasonable?

I'll just check it builds and doesn't break hardware here (I only have
topopoly, not VGA/SVGA hardware), then check in.

Wookey
-- 
Principal hats:  Balloonz - Toby Churchill - Aleph One - Debian
http://wookware.org/