All exposed logic level signals are 3v3. 
and yes it comes from the PXA PSU.
There should be reasonable current capacity (100mA or so)
Its also possible to use VDD_EXT via J9 and switch this to VDD_SPARTAN_IO with J5.
Depending on whats in the FPGA this can give more current.
Alternatively you can tap into VDD_RAW on J13 and regulate down from what ever is incoming, typically 5v.


Regards

David


On 25 May 2011, at 14:31, Patrick Doyle wrote:

> What are the specifications for the I/O voltages on the Balloon board,
> specifically on the SAMOSA connector?
> 
> Looking at the schematic, I see VDD_SAMOSA is sprinkled across J6 & J7
> and that it is attached to VCC_IO through a switch.  I suppose it's
> possible that the supply is dynamically configurable from U5 (a
> MAX_1586B).  I'd have to go look at the data sheet, but I'm really
> more concerned about the IO voltages on that connector.  Are the 3.3V
> or 1.8V?
> 
> For now, I'm going to assume 3.3V, but I hate that word ("assume").
> 
> --wpd
> 
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