Index: Makefile.local
===================================================================
--- Makefile.local	(revision 1572)
+++ Makefile.local	(working copy)
@@ -1,3 +1,5 @@
+export XILINX-TOOLS=/opt/Xilinx/13.1/ISE_DS
+
 $(BUILDDIR)/setup.stamp:
 	mkdir -p $(BUILDDIR) && \
 	mkdir -p $(DISTROBIN) && \
Index: package/vhdl/l3fpga.xst
===================================================================
--- package/vhdl/l3fpga.xst	(revision 1573)
+++ package/vhdl/l3fpga.xst	(working copy)
@@ -1 +1,55 @@
-run -p xc3s1000 -ifmt VHDL -ifn l3fpga.prj -ofn build/fpga/l3fpga.ngc 
\ No newline at end of file
+set -xsthdpdir "build/fpga/xst"
+run
+-ifn l3fpga.prj
+-ifmt mixed
+-ofn build/fpga/l3fpga.ngc
+-ofmt NGC
+-p xc3s1000-5-fg456
+-top l3fpga
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 8
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
Index: package/vhdl/build_fpga
===================================================================
--- package/vhdl/build_fpga	(revision 1573)
+++ package/vhdl/build_fpga	(working copy)
@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash -ex
 
 if [ -z $1 ]; then
   echo -e "No path specified\nSyntax: cpld_build <path to Xilinx tools>"
@@ -9,17 +9,17 @@
 SCRIPTDIR=.
 
 #set up Xilinx tools env vars
-. $1/settings.sh
+. $1/settings32.sh
 
 mkdir -p ${BUILDDIR}
 
 #cd ${BUILDDIR}
-xst -intstyle silent -ifn ${SCRIPTDIR}/l3fpga.xst -ofn ${BUILDDIR}/l3fpga.srp  && \
-ngdbuild -intstyle silent -aul -dd ${BUILDDIR}/ngo -uc ${SOURCEDIR}/l3fpga.ucf \
-  -p xc3s1000 ${BUILDDIR}/l3fpga.ngc ${BUILDDIR}/l3fpga.ngd && \
-map -intstyle silent -cm area -pr b -k 4 -c 100 -tx off -p xc3s1000-5-fg456 \
-  -o ${BUILDDIR}/l3fpga_map.ncd ${BUILDDIR}/l3fpga.ngd ${BUILDDIR}/l3fpga.pcf && \
-par -intstyle silent -w -ol std -t 1 ${BUILDDIR}/l3fpga_map.ncd ${BUILDDIR}/l3fpga.ncd ${BUILDDIR}/l3fpga.pcf && \
-bitgen -intstyle silent ${BUILDDIR}/l3fpga.ncd ${BUILDDIR}/l3fpga.bit
-mv ${BUILDDIR}/l3fpga.bit ${BUILDDIR}/l3fpga.bin
+xst -intstyle silent -ifn ${SCRIPTDIR}/l3fpga.xst -ofn ${BUILDDIR}/l3fpga.syr
 
+ngdbuild -intstyle silent -dd ${BUILDDIR}/ngo -nt timestamp -uc ${SOURCEDIR}/l3fpga.ucf -p xc3s1000-fg456-5 ${BUILDDIR}/l3fpga.ngc ${BUILDDIR}/l3fpga.ngd
+
+map -intstyle silent -p xc3s1000-fg456-5 -cm area -ir off -pr b -c 100 -o ${BUILDDIR}/l3fpga_map.ncd ${BUILDDIR}/l3fpga.ngd ${BUILDDIR}/l3fpga.pcf 
+
+par -w -intstyle silent -ol high -t 1 ${BUILDDIR}/l3fpga_map.ncd ${BUILDDIR}/l3fpga.ncd ${BUILDDIR}/l3fpga.pcf 
+
+bitgen -intstyle silent -f l3fpga.ut ${BUILDDIR}/l3fpga.ncd 
Index: package/vhdl/l3fpga.ut
===================================================================
--- package/vhdl/l3fpga.ut	(revision 0)
+++ package/vhdl/l3fpga.ut	(revision 0)
@@ -0,0 +1,29 @@
+-w
+-g DebugBitstream:No
+-g Binary:yes
+-g CRC:Enable
+-g ConfigRate:6
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
Index: package/vhdl/vhdl.mk
===================================================================
--- package/vhdl/vhdl.mk	(revision 1573)
+++ package/vhdl/vhdl.mk	(working copy)
@@ -1,24 +1,24 @@
 include $(PACKAGEDIR)/vhdl/vhdl.deps
 
-export XILINX-TOOLS=/usr/share/xilinx/
+#export XILINX-TOOLS=/usr/share/xilinx/
 
 ifeq ($(BR2_VHDL_FPGA),y)
 
 fpga-clean:
-	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/vhdl clean)
+	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/package/vhdl clean)
 
 fpga-distclean:
-	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/vhdl distclean)
+	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/package/vhdl distclean)
 
 fpga-dist:
-	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/vhdl dist)
+	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/package/vhdl dist)
 
 fpga-source:
-	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/vhdl source)
+	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/package/vhdl source)
 
 fpga: $(BUILDDIR)/vhdl/vhdl.deps.stamp
 	echo "making fpga"
-	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/vhdl fpga)
+	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/package/vhdl fpga)
 
 TARGETS+=fpga
 
@@ -27,20 +27,20 @@
 
 ifeq ($(BR2_VHDL_CPLD),y)
 cpld-distclean:
-	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/vhdl distclean)
+	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/package/vhdl distclean)
 
 cpld-clean:
-	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/vhdl clean)
+	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/package/vhdl clean)
 
 cpld-dist:
-	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/vhdl dist)
+	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/package/vhdl dist)
 
 cpld-source:
-	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/vhdl source)
+	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/package/vhdl source)
 
 cpld: $(BUILDDIR)/vhdl/vhdl.deps.stamp
 	echo "making cpld"
-	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/vhdl cpld)
+	($(MAKE) $(MAKEOPTS) -C $(CHECKOUT)/package/vhdl cpld)
 
 TARGETS+=cpld
 
Index: package/vhdl/l3fpga.prj
===================================================================
--- package/vhdl/l3fpga.prj	(revision 1573)
+++ package/vhdl/l3fpga.prj	(working copy)
@@ -6,6 +6,6 @@
 vhdl work "./fpga/counter.vhd"
 vhdl work "./fpga/vlio_timer.vhd"
 vhdl work "./fpga/balloon3.vhd"
-vhdl work "./cpld/l3cpld.vhd"
+vhdl work "./fpga/l3fpga.vhd"
 vhdl work "./fpga/Wishbone_Master.vhd"
-vhdl work "./fpga/simple_gpio.v"
+verilog work "./fpga/simple_gpio.v"
Index: package/vhdl/fpga/l3fpga.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: package/vhdl/Makefile
===================================================================
--- package/vhdl/Makefile	(revision 1573)
+++ package/vhdl/Makefile	(working copy)
@@ -1,6 +1,6 @@
 
 TOPLEVEL=../..
-include ../Makefile.inc
+include ../../Makefile.local
 
 #include xilinx_rules.mk
 
@@ -24,27 +24,25 @@
 
 default: cpld fpga
 ifdef XILINX-TOOLS
-	#$(shell . $(XILINX-TOOLS)/settings.sh)
 	./build_cpld $(XILINX-TOOLS) && mv -f l3cpld.jed cpld/
 else
-	# ***************************************************************
-	# ** Your CPLD image is out of date. You need to regenerate it **
-	# **      with the XILINX tools. Specify path to these in      **
-	# **      XILINX-TOOLS in Makefile.local to automate this      **
-	# ***************************************************************
+	@echo "***************************************************************"
+	@echo "** Your CPLD image is out of date. You need to regenerate it **"
+	@echo "**      with the XILINX tools. Specify path to these in      **"
+	@echo "**      XILINX-TOOLS in Makefile.local to automate this      **"
+	@echo "***************************************************************"
 endif
-	
+
 fpga: fpga/l3fpga.bin
 fpga/l3fpga.bin: fpga/l3fpga.vhd $(VHDL-COMMON) $(FPGA-VHDL)
 ifdef XILINX-TOOLS
-	#$(shell . $(XILINX-TOOLS)/settings.sh)
 	./build_fpga $(XILINX-TOOLS) && mv -f build/fpga/l3fpga.bin fpga/
 else
-	# ***************************************************************
-	# ** Your FPGA image is out of date. You need to regenerate it **
-	# **      with the XILINX tools. Specify path to these in      **
-	# **      XILINX-TOOLS in Makefile.local to automate this      **
-	# ***************************************************************
+	@echo "***************************************************************"
+	@echo "** Your FPGA image is out of date. You need to regenerate it **"
+	@echo "**      with the XILINX tools. Specify path to these in      **"
+	@echo "**      XILINX-TOOLS in Makefile.local to automate this      **"
+	@echo "***************************************************************"
 endif
 
 
@@ -64,9 +62,10 @@
 
 clean:
 	rm -rf build
+	rm -rf _xmsgs xlnx_auto_0_xdb *.xrpt
 	rm -rf l3cpld_html
 	rm -f *.chk *.cxt *.gyd *.lso *.jed *.mfd *.pad *.pnx *.rpt *.vm6 *.xml *.csv *.err _impact*
-	rm -f cpld/l3cpld.jed cpld/l3cpld.xsvf cpld/l3cpld.svf
-	rm -f fpga/l3fpga.bin
+	rm -f cpld/l3cpld.svf
+	svn revert cpld/l3cpld.jed cpld/l3cpld.xsvf fpga/l3fpga.bin
 
 .PHONY: all dist clean distclean source