[Yaffs] Re: bit error rates

[Charles Manning]

> 
> > > How YAFFS and YAFFS2 behave?
> > 
> > YAFFS is being more cautious than that, which means that in theory 
> > YAFFS will lose blocks faster than they recommend. However from 
> > accelerated lifetime testing I've done, I have not seen 
> this to be a 
> > practical problem since ECC errors are so rare once the 
> problematic blocks have been removed.
> 
> There is another aspect to that - I've seen yaffs1 leak 
> blocks under power cycling conditions. I suspect power 
> failures were producing incomplete write/erase cycles and ecc 
> errors as a consequence. That led to retirement of good 
> blocks that had bad luck to be written to during power down.
> 
> I would be interested to know if anybody else has seen this behavior.

Curious:

Do you have your write protect pin tied to a power fail flag or such?
The way the wp pin works isharles
 to disable the internal programming voltage generator. The residual
charge might be enough to complete a write, but is not enough to
complete an erase.

If wp is not disabled and the system rails can supply sufficient power
to the NAND chip to complete the erase (~2 to 3 msec) then things should
be fine.

I wonder whether it is worth trying to detect this case and give it
special treatment. The heuristics to do this detection are a bit
boggling.

Charles