[Yaffs] bit error rates --> a vendor speaks

[Claudio Lanconelli]

Thomas Gleixner wrote:

>In general you have to iterate over the data buffer and compute on each
>step. The performance penalty depends on the complexitiy of the
>algortihm. If you have enough space in your FPGA then its definitely a
>good idea to put some ECC calculation mechanism into it. There are
>implementations for both ECC and Reed Solomon available.
>  
>
I made the ECC calculation in FPGA on my system based on SMIL:
http://www.ssfdc.or.jp/english/smil/
it doesn't take much space in FPGA.
I'm interested in Reed Solomon too, where are the implementations available
you are talking about? Can you point me to them, please?

Cheers,
Claudio Lanconelli