Re: [Yaffs] ECC algorithm is hamming code now, will any new …

On Friday 05 August 2005 14:37, zhy78 wrote:
> Will more enhanced algorithm be employed to increasing the performance of
> YAFFS?

There are many ways to measure performance: reliability, write speed, etc.
Which one do you want to measure?

>
> M-systems uses BCH code to support MLC inside its DOC products. This
> algorithm can detect 4bit and correct 4bit error. Will YAFFS employ
> any other new ECC algorithm?

Are the 4 bits 4 bits per page or what? With most ECC structures used with
NAND, the ECC corrects one bad bit per 256 bytes. Correcting more requires
larger ECC areas and requires more ECC computation (hardware or software).

Since ECC is part of mtd (or whatever NAND layer you are using), this is realy
independent of YAFFS.

It is important, when you are considering reliability, to consider the
reliability of the whole solution. From my understanding, DOC will provide
pretty good NAND-level reliability, but if you run FAT on top of that then
you will not get the reliabilkity because FAT is not power safe.

It is also important to consider most likely failure modes. I am not familair
with MLC failure modes, but single bit errors (as corrected by ECC) are
typically very rare with NAND (as used by YAFFS). Double bit errors are even
more rare. I have done done tests a few times where over 100Gbytes of data
was written to a file system without a single bit of corruption. Since
100Gbytes translates into many lifetimes of most mobile/embedded products, I
am pretty confident that for most usages bit errors are not a significant
problem when used with single-bit ECC.

Of course mileage will vary and the experience quoted here might not translate
well to MLC solutions.

-- Charles