>
> I'm looking at using YAFFS in a product we are working on and
> I'm trying to understand the bit error rates of SLC nand devices.
>
> All the docs I've read talk about bit errors that can occur.
> Do these errors occur outside of a write/erase cycle?
> Meaning that if I read the same page 100,000 times am I going
> to get a bit error?
>
> Or are they only due to the oxide layer breakdown that occurs
> during an erase?
Nope.
The worst is the dreaded "program disturb".
I don't believe that there is any "read disturb". Once written, AFAIK
only other writes are likely to mess things up.
Unlike (typical) NOR, you cannot do very many writes to a page. If you
do, you can cause these write disturbs.
YAFFS only does max 1 write per page + 1 write per spare to write a
deletion marker.
YAFFS2 does no rewrites (ie only one write per page and no deletion
markers.
The ECC is also used to help mitigate against this.
NAND flash seems to be getting more reliable all the time. I did some
accelerated lifetime testing where I wrote and verified over 100Gbytes
of data without a single bit being damaged.
>
> Any pointers to clear documentation on this would be appreciated.
The best guide I have read is the Toshiba NAND flash applications design
guide, available at various locations including
http://www.edn.com/contents/images/ToshibaNANDFlash1.pdf
To understand NAND at the level you're talking of, I suggest a
cover-to-cover read of this guide.
>
> Also does anyone here have any experience with using YAFFS
> and an Altera NIOS II setup? I'm not using uCLinux.
YAFFS direct is vanilla C and should compile fine for just about
anything.
>
> Whats the current ram and rom requirements for the direct
> setup (no OS) and a 2k device.
ROM is very architecture dependent. I suggest just building direct off
CVS.
The biggest RAM usage is typically the memory used to build the Tnode
trees. These use ballpark 2 bytes per page of NAND, so for 2kpages you
need about 1k of RAM per 1MB of NAND. Plus expenses :-).
Hope that helps
-- Charles
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