On Friday 15 December 2006 08:48, Andre Renaud wrote:
> We have a system that includes some NAND flash combined together on the
> bus (with some CPLD code to make it appear to be a single chip, and take
> care of combining the ALE,CLE,nCE lines etc...). That is, the 8 data
> bits are combined to give 16, or 32 bits. Thus the chips go from being
> 2k to 4k or 8k, and the OOB size is expanded similarly. Obviously there
> are a few oddities here (such as the bad block marker now being 2 or 4
> markers which each need to be checked), but basically it is just a very
> large NAND chip.
>
> My question is, would there me a huge amount of work involved in
> convincing YAFFS2 to work with a non-standard NAND layout like this?
I'm pretty sure people are already doing this, and I would expect it to "just
work".
As you say, you will need some effort in driver land to get the bad block
markers etc working properly.
The upside:
Faster reads and writes for large files because you're shifting more data per
transaction.
The down side:
Lost space due larger wastage when you are not using a whole chunk.
>
> Thanks,
> Andre
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