On 2008-03-05 10:21 +0000, Chris Jones wrote:
> After a conversation with Nick yesterday, I've made some changes to the
> L3 FPGA code to enable Samosa to work, with a bit of luck. Previously,
> NWP, CLE and ALE were mapped to address lines A23-A21, all of which are
> rather inconveniently defined to be '1' by the FPGA's internal address
> decoding. I've rewired things so that these three lines are on A15-A13
> instead. The Samosa memory map now looks like this:
>
> --SAMOSA Data 8-bit @ 0x10e00004
> --SAMOSA Addr 8-bit @ 0x10e04004
> --SAMOSA Data 16-bit @ 0x10e02004
> --SAMOSA Addr 16-bit @ 0x10e06004
OK. Just to clarify - those are full physical addresses. The offsets
within the FPGA are now:
#define BALLOON3_NANDIO_IO_OFFSET 0x00e00000
#define BALLOON3_PCMCIA0_OFFSET 0x00e00008
#define BALLOON3_PCMCIA1_OFFSET 0x00e00008 /* FIXME same slot for now */
#define BALLOON3_INT_CONTROL_OFFSET 0x00e0000C
#define BALLOON3_NANDIO_CTL2_OFFSET 0x00e00010
#define BALLOON3_NANDIO_CTL_OFFSET 0x00e00014
#define BALLOON3_SAMOSA_DATA8_OFFSET 0x00e00004
#define BALLOON3_SAMOSA_ADDR8_OFFSET 0x00e04004
#define BALLOON3_SAMOSA_DATA16_OFFSET 0x00e02004
#define BALLOON3_SAMOSA_ADDR16_OFFSET 0x00e06004
#define BALLOON3_SAMOSA_CONTROL_OFFSET 0x00e0001c
and full addresses are PXA_CS4_PHYS+above offset
> The lack of fiddling with control register bits should make Samosa
> access a little quicker, too. I haven't actually tested any of this in
> practice, so let me know if there are problems.
Does this mean that the samosa control regsiter now plays no part in
the interface? It certainly doesn't get a mention in the the existing
driver. Can someone tell me what, if anything it does do?
Wookey
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