Firstly I've fixed the FPGA build so NAND now works.
I will check in VHDL changes once I'm happy it's all working.
Once a I get a system to test I'll take a look at PCMCIA as well.
In fact both FPGA and CPLD were completely broken. It appears the VLIO
changes had crept back into Head.
I suspect that the only reason this hasn't come to light on CPLD is that TCL
aren't using HEAD for their CPLD builds.
I'll address some other VHDL points in a further email but my main problem
at the moment is speed.
With my new code and working with an old 3v32 board with 4 x 2G NAND the
time taken to get to a boot prompt after pressing reset (and a space bar) is
17s. Booting from NOR takes ages and from NAND painfully long.
It's just spent 2 hours loading root from a USB stick. (frustratingly a
broken root as it happens.).
I'm guessing a 10 fold speed loss. As far as I can tell this is not VHDL
related.
I'm suspecting YAFFS has slowed down. This may be my build being wrong
somehow, although my experience of incompatible YAFFS version is that it
just breaks.
The code I'm using is from the menuconfig system and kernel 2.6.29-1.
Is it possible that in fixing stuff for 8G NAND and large page sizes we've
slowed it down for 2G small page size?
I'm assuming that the detection of these is automatic and I'm not short of a
compiler flag somewhere?
I'm in the process of chiperase do it all again so in an hour or two I'll
have a system to play with, unless that cures it...
Any Suggestions?
Regards
David
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