RE: [Balloon] PXA270 and FPGA's

>What I'm most interested in is the choice of interface method given that
>the PXA270 allows several [most particularly mapping the FPGA as a
>non-burst SRAM, or mapping it as a VLIO device].

>The latter is most likely going to be needed if the FPGA gates any slow
>hardware since it can assert wait-states (unless you are willing to slow
>down the entire memory region mapped to the FPGA via a MSC register).

>However there are some quirks using the VLIO mode, such as the fact that
>nWE no longer applies (you have to use nPWE for writes, which is normally
>used for the pccard interface. Go figure.)

>Currently on my device* I'm using the non-burst SRAM model with streaming
>data but haven't settled on that as a final solution (application is
>still being developed).

Firstly there is a distinction between the memory interface used to program
the FPGA via the bus from the PXA and the interface implemented in the FPGA
once it is programmed.

L3 uses an SRAM interface with some GPIOS to program the FPGA, the Xilinx
FPGA we are using can accept bytes at about 60MHz so there is little chance
of us timing out on byte writes. (Coupled with the possibility we may need
to bit reverse each byte depending on the use of .bit or .bin files.)

Once the FPGA is up and running its up to the FPGA designer to decide how to
use it (L3 is not application specific so up to a point we don't care how
its used). The L3 FPGA has access to all the control signals so it can
implement VLIO or SRAM or even PCMCIA faking if it wants to.

As you point out the choice comes down to the IO requirements on speed or
synchronisation. On the iTechnic IO system the far side of the FPGA takes
precedence over the bus because it's a sampled system, so the interface is
implemented as VLIO (on L2) simply because the bus does not have guaranteed
access to the internal registers on the FPGA not because the FPGA is slow.

The docs say that nPWE is used for VLIO so as not to interfere with SDRAM
refresh cycles....

Finally why develop a PXA board when there is Loon 2 and soon 3... :-)

Hope this helps

David
iTechnic Ltd.

-- Chris

* not a balloon obviously, but shares some traits with it. I came across
this project via a google search.