Author: Steve Wiseman Date: To: balloon Subject: Re: [Balloon] Bootldr timing update
On Fri Mar 6 15:15 , Chris Jones sent:
>I've done some more fiddling around with memory timings
Ah, this is of interest, if people are fiddling in there. The SDCLK2 signal is
permanently running, and the SDRAM is never poked into idle modes (as far as I
can see). These have EMC implictions - if anyone has alterations they'd like
checked uot in the EMC chamber, let me know.
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