[Yaffs] NAND flash controller computing ecc on main and spar…

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Author: Babrian Viktor
Date:  
To: yaffs
Old-Topics: [Yaffs] General debugging notes
Subject: [Yaffs] NAND flash controller computing ecc on main and spare together
Hi,

I have here a uC with a nand flash controller that computes ECC on the
whole page at once. It has no separate bytes for spare area ECC. Which
means that oob data cannot be written separately. Yaffs is going to be
used on this chip and the question is that does yaffs write oob data
separately? I looked into the sources and I see write_oob() function calls
but I would like to have this confirmed. What possible solutions are there
if oob data has to be written alone? Shall I implement SW ECC on the spare
area and switch off HW ECC when only spare area is accessed?
Or shall I use linux SW ECC and that's it? I would like to avoid sw
overhead if possible.

Any ideas are welcome, thanks,
Viktor Babrian