Re: [Yaffs] MLC support

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Author: Charles Manning
Date:  
To: yaffs
Subject: Re: [Yaffs] MLC support
On Friday 04 December 2009 13:28:39 James Kehl wrote:
> > -----Original Message-----
> > From: [mailto:yaffs-
> > ] On Behalf Of Eddie Dawydiuk
> > Sent: Friday, 4 December 2009 9:53 AM
> > To:
> > Subject: [Yaffs] MLC support
> >
> > Hello,
> >
> > I've seen on the Yaffs homepage it is mentioned MLC support is under
> > development. Although, I've also seen some people on the mailing list
> > already
> > running Yaffs2 on MLC. I'm assuming Yaffs2 will add Reed-Solomon
>
> support
>
> > for
> > MLC, will there be other changes required?
>
> I believe the primary change in Yaffs2 is the avoidance of page
> reprogramming: Yaffs1 needed to clear the 'valid' bit in existing pages
> in order to delete them. Yaffs2 uses a sequence number and an extra
> scan, so each page is programmed once and exactly once (until a block
> erase). MLC likes this better.
>
> I'm pretty sure Yaffs2 does not add Reed-Solomon ECC support *directly*
> - on my particular platform, performing RS in software would chew too
> much CPU, and there's a hardware accelerator instead - but the Yaffs2
> tag structure and larger logical page size makes it actually *possible*
> to use RS ECC when it's implemented by the MTD/NAND driver.


yaffs2 goes a long way towards handling MLC and many yaffs devices use MLC.
MLC handling could be better though. Some particular things that could be
improved:
* Block refreshing to protect against read disturb. There is some work in
progress on this.
* Better handling of error policies with multi-bit errors.

There is no intention to more complex ECC within yaffs. Part of the move to
yaffs2 was to move all ECC out of yaffs into the NAND domain. This caters for
the wide variety of different ECC mechanisms employed in different NAND
controllers/drivers.

BTW: BCH codes are typically superior to RS for NAND error correction. RS is
good for "burst errors" (eg. across radio links), BCH is better for randomly
distributed errors which are more typical in NAND.


Regards

-- Charles