>>OK. It turns out that the problem with this was that it needed a pull-up
on
>>port_en was too feeble, and wasn;t pulling up far enough. Connecting the
>>switch to VDD3 for a good
It would help to know what value was "too feeble" and what was "just right".
>> 3) I can't seem to use the new bflash jtag code on balloon2 at all,
>> either in bflash or jflash mode. It is working for anyone else?
This will not work.
All the code for Balloon 2 is built into jflash, and I have had it working.
However there are a couple of default states (internal to bflash) that are
different between Balloon3 and Balloon2 and the code to context switch them
is not clean, so they were left set for Balloon3 since that is what bflash
was to be used for.
The reason for the unclean-ness is that I have fully parameterised the
settings for Balloon2 and Balloon3 so that simply changing the definition
structs is sufficient to switch processors (and indeed add new ones). The
problem with the existing parameterisation is that there was no easy way to
state if a signal was active high or active low (its default can be set but
not the sense).
This needs to be added. (From memory the signals in question are the bus
enables and you should find some commented out lines that simply invert
these, however until I get back to this in a few weeks I can't put my hand
on my heart and say that by swapping the comments bflash will work for L2.)
>Running LPT ports down cables longer than, wild guess, a foot, is enough
>to make me worry about termination issues.
I have the Xilinx look alike board running on about 1.5-2m of cable without
significant issue, however I have often had to "load" the TCLK line with
47pf to gnd to dampen out the cable ring. I tend to stick this down on the
break out boards without thinking so it have to check to see if it only
works with this mod.
I also remember having to swap the output line defs in playsvx to make it
work with the xilinx dongle however that was about 2 years ago so this may
be a red herring.
David
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