Yes NickB has reported this problem with E1.
I will try and investigate ASAP.
I've checked the schematics and no changes were made to the USB Client
interface between P2 and E1 and the FPGA is not involved in that interface.
I am aware of a detailed issue with the operation of the USB Client
interface which I will consider fixing at the next rev, but I don't think
that this is the problem as the same deficiency existed on P2.
There is always a possibility that this is a software problem....
David
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