Re: [Balloon] Balloon 3 FPGA code?

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Author: Peter Clifton
Date:  
To: Chris Jones
Subject: Re: [Balloon] Balloon 3 FPGA code?

On Thu, 2008-01-24 at 15:50 +0000, Chris Jones wrote:
> David Bisset is the expert on the current expansion boards, but as far
> as I am aware Ethernet controllers and so on live on the system bus. A
> little address decoding should allow your application to live on the
> bus, too.


The application required uncommitted IO lines to be driven as PWM
signals, although I guess since the system bus will be lots faster than
my PWM signals, some addressable latch register could probably do what I
need. The only thing to check, was that I could ensure I got reasonable
latency on the bus.

The PWM signals are to be generated from the FPGA, so it all sounds a
little dodgy though... presumably the CPU is "master" of the bus
normally?

> I hope this is some help,


Its good, thanks.

--
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)