On Thu, 2008-01-24 at 16:36 +0000, David Bisset wrote:
> I assume you are talking about Balloon 3 as Balloon 2 does not strictly have
> a SAMOSA bus.
Yes. I'm at CUED, so have some access to those.
> On Balloon 3 the SAMOSA bus is separate from the CF socket.
> The CF socket shares data and address with the backplane (available over the
> Samtec connector (large 200 way connector on the back)).
>
> There is no conflict between CF and backplane because the PXA treats the CF
> as a separate bus with dedicated control signals (typically labelled
> PCMCI_xxxx or CF_xxxx).
Ok, so data and address lines shared, control lines separate? I see the
CF_xxxx disappear into the FPGA, what are they on the "other side"?
(Is the FPGA source code available for download so I can dig in and have
a look?)
> The "Wired IO" board under development has Ethernet and VGA and USB breakout
> and MMC support (basically making the Balloon a thin client).
> This is now partly working and the hope is to deliver this at the same time,
> or very soon, after the first production run of Balloon 3.
>
> This is all added via the Backplane bus.
>
> There are a number of different ways to get at IO on Balloon 3, depending on
> how much effort/skill you wish to apply.
> a) Use the SAMOSA bus. This can be used as a word bus with muxed address
> latches (actually this is a NAND FLASH type bus) and is typically used to
> access registers on a product motherboard where the backplane (Samtec) is
> not fitted or used. Alternatively the SAMOSA connector can easily be
> refactored inside the FPGA to provide dedicated IO lines either from
> registers or VHDL engines in the FPGA. Since the SAMOSA connector is fitted
> top side this will always be available even on CPLD one side builds.
Sounds useful, but the number of lines available could be limiting
unless I use the latches before the PWM output stage.
> b) Use the Backplane bus and build a dedicated board. Here you will need to
> provide IO drivers and hardware, but this is highly flexible.
(Again, latches etc..)
> c) Use J9 which provides some direct IO from the processor provided you
> don't need the dedicated IO devices that are allocated to it.
The plan was to implement the PWM control in the FPGA to do stuff like
timing and fault-protection in as raw logic as possible. (Hence my
slight caution about using an addressed bus with latches, rather than
driving the PWM lines directly).
> Ironically the FPGA we are fitting has far more IO pins than we have space
> to route so there are quite a few IO lines from it that just terminate on
> vias from the FPGA ball array. I am in the process of laying out the final
> production version of the board and one task is to see if there is any way
> to expose these sensibly, but don't hold your breath...
Its a shame to waste good IO lines, but I appreciate the Balloon board
is pretty crammed already.
> I will also publish the schematic for the Backplane interface and the
> associated blank motherboard. These will be in Protel format but have the
> advantage that a real board has been made from them and so the bug level is
> lower.
Could you send me a pdf of the motherboard schematic? (So I can get a
feel for how ethernet etc.. is done. I've not worked on any serious
digital IO / computer design before.)
> Finally you ask about on-board Ethernet. There are good reasons not to do
> this in the next rev. One reason the Balloon format is so nice is that there
> are no large connectors eating up board space. Because there are reasonable
> constraints on the layout and routing of Ethernet line signals (potentially
> 240v and high speed) from the driver chip to the transformer and on to the
> massive RJ45 connector the addition of on-board ether will eat a very
> significant fraction of the Balloon board real estate, not to mention the
> vast increase in board height and the limitations on placing the Balloon
> board in equipment cause by having the Ethernet connector in a fixed
> location.
Presumably you'd use a dongle with the connector, such as with PCMCIA
ethernet cards. I'm kind-of surprised you need 240v isolation rules
after the 4kV(?) rated isolation transformer, but I take your word as
expert here. Can the magnetics live in the dongle?
> For all these reasons the Ethernet will be provided via an attached IO board
> so that people can refactor the location and fit of the massive connectors
> we have inherited from the 1990's. (Rant over :-))
Only thing wrong with RJ45 IMO, is the tendency for the latching tab to
break off when teasing wires out of tangles. They meet connector
desirability metric No.1, and make a very satisfying click when mated.
> Given that the design phase of Balloon 3 is now effectively over we are
> starting to think about Balloon 4. So Suggestions are welcome...
> Please also bear in mind that we *may* move away from Marvel as the core
> processor vendor given that their documentation is not freely available and
> it looks a bit odd having an open hardware project where the information
> about the core processing element is not openly available.
> David Bisset
> MD Balloonz
Thanks for your help,
Best wishes,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
(text/plain)